| Presentation | 2008-03-07 A Low-cost Speed and Yield Enhancement Method using Enbedded Delay-Detectors on FPGAs Yohei KUME, Yuuri SUGIHARA, Ngo CAM LAI, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper shows the principle and architecture of a low-cost speed and yield enhancement method using enbedded delay detectors on FPGAs. we apply critical path reconfiguration to utilize random variations for performance enhancement. We have to know which path is faster on the critical path reconfiguration, but the cost of measurement by path-delay measurement method is very large. In order to search for faster paths with much lower cost, we propose measurement method using delay detectors. Computing measurement cost by delay detectors can be treated as an edge-coloring probelem. The cost is equal edge-color number κ. The order of κ is derived from the upper and lower bound of the measurment cost. k is independent of the circuit size and turned out to be constant. The computation time for this algorithm is O (n) where n is the number of CLBs in the critical path candidates. By implementing and applying this algorithm to a set of benchmark circuits we verified that the measurment cost is close to the lower bound. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGA / Variation-aware / Yield Enhancement |
| Paper # | VLD2007-163,ICD2007-186 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/2/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Low-cost Speed and Yield Enhancement Method using Enbedded Delay-Detectors on FPGAs |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | Variation-aware |
| Keyword(3) | Yield Enhancement |
| 1st Author's Name | Yohei KUME |
| 1st Author's Affiliation | Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Yuuri SUGIHARA |
| 2nd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 3rd Author's Name | Ngo CAM LAI |
| 3rd Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 4th Author's Name | Kazutoshi KOBAYASHI |
| 4th Author's Affiliation | Graduate School of Informatics, Kyoto University |
| 5th Author's Name | Hidetoshi ONODERA |
| 5th Author's Affiliation | Graduate School of Informatics, Kyoto University |
| Date | 2008-03-07 |
| Paper # | VLD2007-163,ICD2007-186 |
| Volume (vol) | vol.107 |
| Number (no) | 508 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |