| Presentation | 2008-03-07 A Self-timed Processor with Dynamic Voltage Scaling Taku SOGABE, Makoto IKEDA, Kunihiro Asada, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As PVT variations get larger, synchronous circuits are getting less reliable and timing margins are getting larger. Self-timed circuits based on a completion-detection architecture detect completion of each executions. A variation of delay doesn't cause any error in these circuits. DCVSL using dual-rail logic can implement them, so the way to design a processor automatically is established. A processor is designed in this way. It can follow a target speed with dynamic voltage scaling. The operating speed of a self-timed processor is average of delays, so it is faster than the largest delay. This difference of delays is used as power saving when the processor is operated with synchronous circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Asynchronous Circuit / Dual-rail Logic / DCVSL / Dynamic Voltage Scaling |
| Paper # | VLD2007-158,ICD2007-181 |
| Date of Issue |
| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/2/29(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Self-timed Processor with Dynamic Voltage Scaling |
| Sub Title (in English) | |
| Keyword(1) | Asynchronous Circuit |
| Keyword(2) | Dual-rail Logic |
| Keyword(3) | DCVSL |
| Keyword(4) | Dynamic Voltage Scaling |
| 1st Author's Name | Taku SOGABE |
| 1st Author's Affiliation | The University of Tokyo() |
| 2nd Author's Name | Makoto IKEDA |
| 2nd Author's Affiliation | The University of Tokyo |
| 3rd Author's Name | Kunihiro Asada |
| 3rd Author's Affiliation | The University of Tokyo |
| Date | 2008-03-07 |
| Paper # | VLD2007-158,ICD2007-181 |
| Volume (vol) | vol.107 |
| Number (no) | 508 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |