Presentation | 2008-03-07 A delay balancing technique for wave-pipelining Keiichiro SANO, Jubee TADA, Ryusuke EGAWA, Gensuke GOTO, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Wave pipeline is a cutting-edge technology as an alternative to traditional pipeline, However, wave pipelining requires the precise delay control, in tern, wave-pipelined circuits require all paths between the inputs and outputs to be balanced. So far, design methods for wave pipelined circuits under recent CMOS technologies have not yet established well compared with those for conventional pipelines. To overcome this situation, we propose a delay balancing technique with delay elements insertion and gain-based gate sizing. Experimental results show that our approach achieves up to 12 times higher clock rate and reduces up to 28% power-delay product. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Wave pipeline / delay balancing |
Paper # | VLD2007-156,ICD2007-179 |
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Committee | VLD |
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Conference Date | 2008/2/29(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | A delay balancing technique for wave-pipelining |
Sub Title (in English) | |
Keyword(1) | Wave pipeline |
Keyword(2) | delay balancing |
1st Author's Name | Keiichiro SANO |
1st Author's Affiliation | Yamagata University() |
2nd Author's Name | Jubee TADA |
2nd Author's Affiliation | Yamagata University |
3rd Author's Name | Ryusuke EGAWA |
3rd Author's Affiliation | Touhoku University |
4th Author's Name | Gensuke GOTO |
4th Author's Affiliation | Yamagata University |
Date | 2008-03-07 |
Paper # | VLD2007-156,ICD2007-179 |
Volume (vol) | vol.107 |
Number (no) | 508 |
Page | pp.pp.- |
#Pages | 6 |
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