Presentation 2008-03-06
A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration
Tetsuro IKEDA, Atsushi IWATA,
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Abstract(in English) This paper proposes a high-accuracy and low-power cyclic ADC using digital calibration technique. By using a cascaded cyclic ADC, we can reduce an operation speed of unit circuit and power consumption. To acieve high accuracy, new digital calibration algorithm to compensate capacitance mismatch of a switched capacitor gain stage was proposed. Utilizing the propsed ADC architecture, a 2-stage cyclic ADC with 16 bit resolution was designed using a 0.18μm CMOS technology. The ADC opeartes at 500kS/s sampling rate with 20mW power dissipation. The efffects of digtal calibration was confirmed by simulation. A calibrated Integral Non Linearity (INL) was about ±3 LSB of 16 bit.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Cyclic ADC / Switched capacitor circuit / Digital calibration
Paper # VLD2007-144,ICD2007-167
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Conference Information
Committee VLD
Conference Date 2008/2/28(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration
Sub Title (in English)
Keyword(1) Cyclic ADC
Keyword(2) Switched capacitor circuit
Keyword(3) Digital calibration
1st Author's Name Tetsuro IKEDA
1st Author's Affiliation Graduate School of Advanced Science of Matter, Hiroshima University.()
2nd Author's Name Atsushi IWATA
2nd Author's Affiliation Graduate School of Advanced Science of Matter, Hiroshima University.
Date 2008-03-06
Paper # VLD2007-144,ICD2007-167
Volume (vol) vol.107
Number (no) 507
Page pp.pp.-
#Pages 6
Date of Issue