Presentation | 2008-03-05 Analog Floorplan with Soft-Module Configuration Kentaro MURATA, Kazuya SASAKI, Qing DONG, Jing LI, Shigetoshi NAKATAKE, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In MOS analog design, the transistor size is increasing as the supply voltage becomes lower, and the layout configuration of the transistor module is diversified. In this paper, we propose a novel analog floorplan technique for dealing with modules with discrete outline candidates. In our floorplan, rectangular local structures are extracted from a given sequence-pair, and the aspect ratio of every module included in the structure is changed at the same time by an equal scaling ratio for minimizing the chip area. In experiments, the results showed the advantage of our floorplan technique. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Floorplan / Soft-Module / Sequence-Pair |
Paper # | VLD2007-142,ICD2007-165 |
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Committee | VLD |
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Conference Date | 2008/2/27(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Analog Floorplan with Soft-Module Configuration |
Sub Title (in English) | |
Keyword(1) | Floorplan |
Keyword(2) | Soft-Module |
Keyword(3) | Sequence-Pair |
1st Author's Name | Kentaro MURATA |
1st Author's Affiliation | Shool of Environmental Engineering, University of Kitakyushu() |
2nd Author's Name | Kazuya SASAKI |
2nd Author's Affiliation | Shool of Environmental Engineering, University of Kitakyushu |
3rd Author's Name | Qing DONG |
3rd Author's Affiliation | Shool of Environmental Engineering, University of Kitakyushu |
4th Author's Name | Jing LI |
4th Author's Affiliation | Shool of Environmental Engineering, University of Kitakyushu |
5th Author's Name | Shigetoshi NAKATAKE |
5th Author's Affiliation | Shool of Environmental Engineering, University of Kitakyushu |
Date | 2008-03-05 |
Paper # | VLD2007-142,ICD2007-165 |
Volume (vol) | vol.107 |
Number (no) | 506 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |