| Presentation | 2008-03-05 An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory Shunitsu KOHARA, Youhua SHI, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | This paper proposes an energy-efficient ASIP synthesis method based on reducing bit-width of instruction memory. VLIW-type processors can execute several instructions concurrently. However, an instruction memory of the processors requires long bit-width. This increases power and energy consumption wastefully. Therefore reducing bit-width of instruction memory can realize high-performance and energy-efficient processors. Bit-width of an instruction memory depends on the instruction encoding format, which is composed of the opcode and the operands of a instruction. The opcode bit-width depends on the number of instructions in the instruction-set and the operand bit-width depends depends on the number of general-purpose registers. Moreover, to reduce opcode bit-width, we introduce a concept of a combined instruction which is handled as one instruction and composed of several instructions issued concurrently at each VLIW-slots. We develop an energy-efficient ASIP synthesis system including 3 algorithm: opcode bit-width reduction algorithm, operand bit-width reduction algorithm and energy minimization algorithm. In experimental results, we confirm 9%～12% energy consumption reduction at a whole processor system including memories. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | ASIP / energy consumption / energy optimization / instruction-set / instruction memory |
| Paper # | VLD2007-141,ICD2007-164 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/2/27(1days) |
| Place (in Japanese) | (See Japanese page) |
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| Topics (in Japanese) | (See Japanese page) |
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| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Energy-efficent ASIP Synthesis Method Based on Reducing Bit-width of Instruction Memory |
| Sub Title (in English) | |
| Keyword(1) | ASIP |
| Keyword(2) | energy consumption |
| Keyword(3) | energy optimization |
| Keyword(4) | instruction-set |
| Keyword(5) | instruction memory |
| 1st Author's Name | Shunitsu KOHARA |
| 1st Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University() |
| 2nd Author's Name | Youhua SHI |
| 2nd Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 3rd Author's Name | Nozomu TOGAWA |
| 3rd Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| 4th Author's Name | Masao YANAGISAWA |
| 4th Author's Affiliation | Dept. of Electronic and Photonic Systems, Waseda University |
| 5th Author's Name | Tatsuo OHTSUKI |
| 5th Author's Affiliation | Dept. of Computer Science and Engineering, Waseda University |
| Date | 2008-03-05 |
| Paper # | VLD2007-141,ICD2007-164 |
| Volume (vol) | vol.107 |
| Number (no) | 506 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |