Presentation 2008-03-05
Automatic synthesis and verification of practical protocol transducer based on product graph exploration
Yuji ISHIKAWA, Satoshi KOMATSU, Masahiro FUJITA,
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Abstract(in English) To design system LSIs using existing designs, we need protocol transducers, which convert one on-chip communication protocol into another. However, automatic protocol transducer synthesis methods are not incorporated to design flows of LSIs, because they cannot handle today's practical protocols and generated transducers are not reliable enough. In this paper, we propose an automatic transducer synthesis method which can handle real-life protocols. Our method is based on existing researches of product graph exploration method. Also we propose a verification method to improve reliablity of generated transducers.
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Keyword(in English) Design Reuse / On-chip Communication / Protocol Transducer / Graph Exploration
Paper # VLD2007-137,ICD2007-160
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Committee VLD
Conference Date 2008/2/27(1days)
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Registration To VLSI Design Technologies (VLD)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Automatic synthesis and verification of practical protocol transducer based on product graph exploration
Sub Title (in English)
Keyword(1) Design Reuse
Keyword(2) On-chip Communication
Keyword(3) Protocol Transducer
Keyword(4) Graph Exploration
1st Author's Name Yuji ISHIKAWA
1st Author's Affiliation Department of Electronics Engineering, School of Engineering, University of Tokyo()
2nd Author's Name Satoshi KOMATSU
2nd Author's Affiliation VLSI Design and Education Center, University of Tokyo
3rd Author's Name Masahiro FUJITA
3rd Author's Affiliation VLSI Design and Education Center, University of Tokyo
Date 2008-03-05
Paper # VLD2007-137,ICD2007-160
Volume (vol) vol.107
Number (no) 506
Page pp.pp.-
#Pages 6
Date of Issue