Presentation 2008-07-31
An Efficient Memory Access System for Array Processor in wireless communication system
Tomoyoshi KOBORI, Katsutoshi SEKI, James OKELLO, Masao IKEKAWA,
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Abstract(in English) This paper describes the efficient memory access system for array processor in wireless communication system. Today, there are many studies for array processing in wireless communication system for next generation wireless access such as WLAN, WiMAX, LTE, and so on because of processing complexity for matrix calculation. We proposed memory access system "Multithread Interleaving" which target is such an array processor. To achieve higher performance and higher flexibility, Multithread interleaving can perform to reduce the amount of inter-bank data transfer. The memory IF and address generation unit which include RISC like processor and dedicated HW unit are needed for this method. In case of 256point FFT, proposed system can reduced about 13% of processing time compared with traditional address generation system.
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Keyword(in English) OFDM / FFT / Systlic Array / memory access / reconfigurable
Paper # SR2008-23
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Conference Date 2008/7/24(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) An Efficient Memory Access System for Array Processor in wireless communication system
Sub Title (in English)
Keyword(1) OFDM
Keyword(2) FFT
Keyword(3) Systlic Array
Keyword(4) memory access
Keyword(5) reconfigurable
1st Author's Name Tomoyoshi KOBORI
1st Author's Affiliation System IP Core Res Lab, NEC Corp.()
2nd Author's Name Katsutoshi SEKI
2nd Author's Affiliation System IP Core Res Lab, NEC Corp.
3rd Author's Name James OKELLO
3rd Author's Affiliation System IP Core Res Lab, NEC Corp.
4th Author's Name Masao IKEKAWA
4th Author's Affiliation System IP Core Res Lab, NEC Corp.
Date 2008-07-31
Paper # SR2008-23
Volume (vol) vol.108
Number (no) 172
Page pp.pp.-
#Pages 6
Date of Issue