| Presentation | 2008-06-20 Note on Hardware Overhead and Fault Location for Memory BIST Masayuki ARAI, Kentaro OSAWA, Kazuhiko IWASAKI, Michinobu NAKAO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Memory BIST (Built-in Self-Test) is one of the effective scheme for test cost reduction of embedded SRAM. In the BIST architecture, comparators are used to compare the output from the SRAM with the expected values. When multiple SRAMs are embedded in an SoC, it is difficult to share one comparator with all of the SRAMs. Therefore, the hardware overhead of comparators tends to increase significantly as the number of SRAMs increases, and thus the hardware overhead reduction for the comparators is an important problem. In this study we discuss the hardware overhead reduction for memory BIST by applying encoder-based comparator. We apply two encoders, the one is priority encoder and another is OR-based encoder, and evaluate the hardware overhead. We also consider the case that fault location information obtained by the proposed architecture is used by a repair logic, and evaluate the yield by the simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | memory BIST / BISR / repair logic / embedded SRAM |
| Paper # | DC2008-18 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2008/6/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Vice Chair | |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Note on Hardware Overhead and Fault Location for Memory BIST |
| Sub Title (in English) | |
| Keyword(1) | memory BIST |
| Keyword(2) | BISR |
| Keyword(3) | repair logic |
| Keyword(4) | embedded SRAM |
| 1st Author's Name | Masayuki ARAI |
| 1st Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University() |
| 2nd Author's Name | Kentaro OSAWA |
| 2nd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
| 3rd Author's Name | Kazuhiko IWASAKI |
| 3rd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
| 4th Author's Name | Michinobu NAKAO |
| 4th Author's Affiliation | Renesas Technology Inc. |
| Date | 2008-06-20 |
| Paper # | DC2008-18 |
| Volume (vol) | vol.108 |
| Number (no) | 99 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |