Presentation	2008-06-20 The State of the Art and Future Trends of Test Design Yasuo SATO,
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Abstract(in English)	As the manufacturing process evolves with shrinking geometry and the speed of an LSI circuit increases, LSI testing technologies are required various changes qualitatively and quantitatively. The conventional tests, such as the stuck-at fault test, which finds LSI's pass/fail deterministically, are no more major solutions, and the various parametric tests, which find LSI's pass/fail statistically, became crucial. These statistical approaches are essentially different from the conventional ones. It also became crucial how to reduce test cost as long as suppressing the increase of the number of test patterns or the amount of test data. In this paper, we show the state of the art and future trends of DFT design based on the latest researches and ITRS (International Technology Roadmap for Semiconductors).
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Test pattern count / Test data amount / Parametric test / Test cost
Paper #	DC2008-15
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Conference Information
Committee	DC
Conference Date	2008/6/13(1days)
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Paper Information
Registration To	Dependable Computing (DC)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	The State of the Art and Future Trends of Test Design
Sub Title (in English)
Keyword(1)	Test pattern count
Keyword(2)	Test data amount
Keyword(3)	Parametric test
Keyword(4)	Test cost
1st Author's Name	Yasuo SATO
1st Author's Affiliation	Hitachi, Ltd. Micro Device Division()
Date	2008-06-20
Paper #	DC2008-15
Volume (vol)	vol.108
Number (no)	99
Page	pp.pp.-
#Pages	5
Date of Issue