| Presentation | 2008-06-20 Test generation for multi-operand adders consisting of full adders Nobutaka KITO, Naofumi TAKAGI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Level-testability of multi-operand adders consisting of carry save adders is shown by showing test design for it. Carry save adders consists of full adders. A multi-operand adder is a main component of a multiplier. 6L+2 patterns are sufficient to test a multi-operand adder under cell fault model, where L denotes the height of the multi-operand adder. A test method of the multi-operand adder in a multiplier is also shown. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | multi-operand adder / multiplier / Wallace multiplier / level-testability |
| Paper # | DC2008-14 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2008/6/13(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Test generation for multi-operand adders consisting of full adders |
| Sub Title (in English) | |
| Keyword(1) | multi-operand adder |
| Keyword(2) | multiplier |
| Keyword(3) | Wallace multiplier |
| Keyword(4) | level-testability |
| 1st Author's Name | Nobutaka KITO |
| 1st Author's Affiliation | Department of Information Engineering, Nagoya University() |
| 2nd Author's Name | Naofumi TAKAGI |
| 2nd Author's Affiliation | Department of Information Engineering, Nagoya University |
| Date | 2008-06-20 |
| Paper # | DC2008-14 |
| Volume (vol) | vol.108 |
| Number (no) | 99 |
| Page | pp.pp.- |
| #Pages | 4 |
| Date of Issue | |