Presentation 2008-06-20
A Design of Highly Dependable Processor with the Tolerance to Multiple Simultaneous Transient Faults
Makoto KIMURA, Masayuki ARAI, Satoshi FUKUMOTO, Kazuhiko IWASAKI,
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Abstract(in English) We propose the methodology to make a highly reliable processor against multiple simultaneous transient faults. In our proposal, the electromagnetic waves caused by short-circuit discharge of a capacitor is adopted as fault model. Since the basic concept of our methodology is space and time redundancy, we expected notable improvement of dependability in exchange for hardware and performance overheads. We applied the methodology to the processor described by VHDL and evaluated its reliability by logic simulation considering the recovery rate against activated errors as a reliability evaluation measure.
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Keyword(in English) Transient Fault / Multiple Simultaneous Faults / Highly Dependable Processor
Paper # DC2008-13
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Committee DC
Conference Date 2008/6/13(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Design of Highly Dependable Processor with the Tolerance to Multiple Simultaneous Transient Faults
Sub Title (in English)
Keyword(1) Transient Fault
Keyword(2) Multiple Simultaneous Faults
Keyword(3) Highly Dependable Processor
1st Author's Name Makoto KIMURA
1st Author's Affiliation Faculty of System Design, Tokyo Metropolitan University()
2nd Author's Name Masayuki ARAI
2nd Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
3rd Author's Name Satoshi FUKUMOTO
3rd Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
4th Author's Name Kazuhiko IWASAKI
4th Author's Affiliation Graduate School of System Design, Tokyo Metropolitan University
Date 2008-06-20
Paper # DC2008-13
Volume (vol) vol.108
Number (no) 99
Page pp.pp.-
#Pages 6
Date of Issue