| Presentation | 2008-06-13 An Architecture of Photo Core Transform in HD Photo Coding System for Embedded Systems of Various Bandwidths Koichi HATTORI, Hiroshi TSUTSUI, Hiroyuki OCHI, Yukihiro NAKAMURA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image data into frequency domain in HD Photo, an emerging image coding system developed by Microsoft. In order to support various memory bus bandwidths used in system-on-a-chip (SoC) design, an implementation for each bandwidth can be derived based on our architecture. In addition, in order to reduce the local memory size and the traffic between the main and local memories, we propose a novel data transfer and storing scheme for PCT. The experimental results show that hardware modules corresponding to the given bus bandwidths can be reasonably derived from the proposed architecture. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | HD Photo / JPEG XR / Photo Core Transform / Embedded systems / Image coding / IP core / Pipeline processing / Architecture exploration |
| Paper # | SIS2008-21 |
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| Conference Information | |
| Committee | SIS |
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| Conference Date | 2008/6/6(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
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| Paper Information | |
| Registration To | Smart Info-Media Systems (SIS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Architecture of Photo Core Transform in HD Photo Coding System for Embedded Systems of Various Bandwidths |
| Sub Title (in English) | |
| Keyword(1) | HD Photo |
| Keyword(2) | JPEG XR |
| Keyword(3) | Photo Core Transform |
| Keyword(4) | Embedded systems |
| Keyword(5) | Image coding |
| Keyword(6) | IP core |
| Keyword(7) | Pipeline processing |
| Keyword(8) | Architecture exploration |
| 1st Author's Name | Koichi HATTORI |
| 1st Author's Affiliation | Dept. of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University() |
| 2nd Author's Name | Hiroshi TSUTSUI |
| 2nd Author's Affiliation | Dept. of Information Systems Engineering, Graduate School of Information Science and Technology, Osaka University |
| 3rd Author's Name | Hiroyuki OCHI |
| 3rd Author's Affiliation | Dept. of Communications and Computer Engineering, Graduate School of Informatics, Kyoto University |
| 4th Author's Name | Yukihiro NAKAMURA |
| 4th Author's Affiliation | Research Organization of Science and Engineering, Ritsumeikan University |
| Date | 2008-06-13 |
| Paper # | SIS2008-21 |
| Volume (vol) | vol.108 |
| Number (no) | 86 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |