Presentation | 2008-06-12 VLSI Architecture of a Pipelined MMSE Detector in a 4×4 MIMO-OFDM Receiver Shingo YOSHIZAWA, Yoshikazu MIYANAGA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | This report presents a VLSI architecture of MMSE detection in a 4×4 MIMO-OFDM receiver. Pack-et-based MIMO-OFDM imposes a considerable throughput requirement on the matrix inversion because of strict timing in frame structure and subcarrier-by-subcarrier basis processing. Pipeline processing oriented algorithms are preferable to tackle this issue. We propose a pipelined MMSE detector using Strassen's algorithms of matrix inversion and multiplication. This circuit achieves real-time operation which does not depend on numbers of subcarriers. The designed circuit has been implemented to a 90-nm CMOS process and evaluated in processing latency, circuit area, and power consumption. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | MIMO-OFDM / MIMO Decoder / MMSE Detection / VLSI Architecture |
Paper # | SIS2008-9 |
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Committee | SIS |
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Conference Date | 2008/6/5(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Smart Info-Media Systems (SIS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | VLSI Architecture of a Pipelined MMSE Detector in a 4×4 MIMO-OFDM Receiver |
Sub Title (in English) | |
Keyword(1) | MIMO-OFDM |
Keyword(2) | MIMO Decoder |
Keyword(3) | MMSE Detection |
Keyword(4) | VLSI Architecture |
1st Author's Name | Shingo YOSHIZAWA |
1st Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University() |
2nd Author's Name | Yoshikazu MIYANAGA |
2nd Author's Affiliation | Graduate School of Information Science and Technology, Hokkaido University |
Date | 2008-06-12 |
Paper # | SIS2008-9 |
Volume (vol) | vol.108 |
Number (no) | 85 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |