| Presentation | 2008-06-27 On the Test Environment Generation Problem Using Assignment Decision Diagrams Yuki SHIMIZU, Chia Yee OOI, Hideo FUJIWARA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we consider a problem of test environment generation for functional register-transfer level (RTL) circuits using an assignment decision diagram (ADD). As for the test environment generation method using ADDs, Ghosh et al. and Zhang et al. proposed symbolic processing based algorithms which utilize a set of 9-valued and 10-valued algebras, respectively, to perform symbolic justification and propagation of test objectives. However, it is known that there are many cases that their methods fail to generate a test environment even if it exists. This paper presents a new method for test environment generation with enhanced symbolic processing (justification and propagation) rules in order to generate more test environments than previous methods. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Test environment / RTL test generation / high-level testing / assignment decision diagrams |
| Paper # | CAS2008-22,VLD2008-35,SIP2008-56 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On the Test Environment Generation Problem Using Assignment Decision Diagrams |
| Sub Title (in English) | |
| Keyword(1) | Test environment |
| Keyword(2) | RTL test generation |
| Keyword(3) | high-level testing |
| Keyword(4) | assignment decision diagrams |
| 1st Author's Name | Yuki SHIMIZU |
| 1st Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology() |
| 2nd Author's Name | Chia Yee OOI |
| 2nd Author's Affiliation | Faculity of Electrical Engineering University of Technology Malaysia |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science Nara Institute of Science and Technology |
| Date | 2008-06-27 |
| Paper # | CAS2008-22,VLD2008-35,SIP2008-56 |
| Volume (vol) | vol.108 |
| Number (no) | 107 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |