| Presentation | 2008-06-27 An Approach to RTL-GL Path Mapping Based on Functional Equivalence Hiroshi IWATA, Satoshi OHTAKE, Hideo FUJIWARA, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Information on false paths in a circuit is useful for design and test. The use of this information may contribute not only in reducing the time required for logic synthesis, the area, the test generation time and the test application time of the circuit but also in alleviating the over-testing. Since identification of false paths at gate-level is hard for large circuits with huge number of paths, several methods using high-level design information have been proposed. These methods are effective only if the correspondence between paths at register transfer level (RTL) and those at gate-level is available. Until now, the correspondence has been established only by module interface preserving-logic synthesis. In this paper, we propose a method of mapping an RTL path to the gate-level paths without restricting the logic synthesis. The method first maps each bit slice RTL signal line of an RTL path to a gate level signal line by considering the functional equivalence of those signal lines. Then the RTL path is mapped to gate level paths using these correspondences. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | path mapping / register transfer level / gate-level / functional equivalence / fault diagnosis |
| Paper # | CAS2008-21,VLD2008-34,SIP2008-55 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Approach to RTL-GL Path Mapping Based on Functional Equivalence |
| Sub Title (in English) | |
| Keyword(1) | path mapping |
| Keyword(2) | register transfer level |
| Keyword(3) | gate-level |
| Keyword(4) | functional equivalence |
| Keyword(5) | fault diagnosis |
| 1st Author's Name | Hiroshi IWATA |
| 1st Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology() |
| 2nd Author's Name | Satoshi OHTAKE |
| 2nd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| 3rd Author's Name | Hideo FUJIWARA |
| 3rd Author's Affiliation | Graduate School of Information Science, Nara Institute of Science and Technology |
| Date | 2008-06-27 |
| Paper # | CAS2008-21,VLD2008-34,SIP2008-55 |
| Volume (vol) | vol.108 |
| Number (no) | 107 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |