| Presentation | 2008-06-27 Safe Clocking Minimum Register Assignment in High-Level Synthesis Keisuke INOUE, Mineo KANEKO, Tsuyoshi IWAGAKI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | For recent and future nanometer-technology VLSIs, static and dynamic delay variations become a serious problem. In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. Our approach to delay variation (in particular, the hold constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by the contra-data-direction (CDD) clocking. After formulating this new register assignment problem, we prove it to be NP-hard, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by CDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | High-level synthesis / hold constraint / safe clocking / register assignment / integer linear programming |
| Paper # | CAS2008-20,VLD2008-33,SIP2008-54 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/6/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Safe Clocking Minimum Register Assignment in High-Level Synthesis |
| Sub Title (in English) | |
| Keyword(1) | High-level synthesis |
| Keyword(2) | hold constraint |
| Keyword(3) | safe clocking |
| Keyword(4) | register assignment |
| Keyword(5) | integer linear programming |
| 1st Author's Name | Keisuke INOUE |
| 1st Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST)() |
| 2nd Author's Name | Mineo KANEKO |
| 2nd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST) |
| 3rd Author's Name | Tsuyoshi IWAGAKI |
| 3rd Author's Affiliation | School of Information Science, Japan Advanced Institute of Science and Technology (JAIST) |
| Date | 2008-06-27 |
| Paper # | CAS2008-20,VLD2008-33,SIP2008-54 |
| Volume (vol) | vol.108 |
| Number (no) | 107 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |