| Presentation | 2008-06-26 A Lateral Unified-CBiCMOS Buffer Circuit for High Speed and Low Energy Based on 0.18μmCMOS/SOI Process Takashi HAMAHATA, Satoshi UTO, Toshiro AKINO, Kenji NISHI, Kohsei TAKEHARA, T. Goji ETOH, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we develop a printed circuit board having a discrete device that can drive a CCD chip with 5nF maximum load capacitance per CCD clock at a high speed of 100MHz and design a voltage source chip to generate the clock on basis of 0.18μmCMOS/SOI process. Although we are based on a set of BSIM3 model parameters from a TSMC bulk CMOS process, we modify the substrate doping from a non-uniform diffusion profile with the TSMC channel doping to a uniform profile of the same channel doping along a direction of deep SOI substrate. As we try to make a substrate terminal to be non-floating and design a compact layout in order to reduce the resistance value of substrate interconnection, we optimize the size of unified-CBiCMOS buffer circuit for a high speed and low energy operation of lateral npn-and pnp-BJTs. We fix the absolute value of threshold voltage as 0.5V and then the ratio value of 【power supply voltage/threshold voltage】 is changed from 1.5 to 4. As a result of circuit simulation, the minimum average energy of the unified-CBiCMOS buffer circuit is around at the ratio value of 2. Furthermore, we report the circuit simulation results under various conditions. It is concluded that a technical outlook of clock generation around 100MHz is established by the circuit simulation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | BJT / CBiCMOS / CMOS/SOI / TSMC / BSIM3 |
| Paper # | CAS2008-16,VLD2008-29,SIP2008-50 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2008/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Lateral Unified-CBiCMOS Buffer Circuit for High Speed and Low Energy Based on 0.18μmCMOS/SOI Process |
| Sub Title (in English) | |
| Keyword(1) | BJT |
| Keyword(2) | CBiCMOS |
| Keyword(3) | CMOS/SOI |
| Keyword(4) | TSMC |
| Keyword(5) | BSIM3 |
| 1st Author's Name | Takashi HAMAHATA |
| 1st Author's Affiliation | School of Biology-Oriented Science and Technology, Kinki University() |
| 2nd Author's Name | Satoshi UTO |
| 2nd Author's Affiliation | School of Biology-Oriented Science and Technology, Kinki University |
| 3rd Author's Name | Toshiro AKINO |
| 3rd Author's Affiliation | School of Biology-Oriented Science and Technology, Kinki University |
| 4th Author's Name | Kenji NISHI |
| 4th Author's Affiliation | Kinki University Technology College |
| 5th Author's Name | Kohsei TAKEHARA |
| 5th Author's Affiliation | School of Science and Engineering, Kinki University |
| 6th Author's Name | T. Goji ETOH |
| 6th Author's Affiliation | School of Science and Engineering, Kinki University |
| Date | 2008-06-26 |
| Paper # | CAS2008-16,VLD2008-29,SIP2008-50 |
| Volume (vol) | vol.108 |
| Number (no) | 104 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |