| Presentation | 2008-06-26 Power Supply Chip for CCD in Ultra-High-Speed Camera Based on 1.2-μmCMOS/SOI Process with High Breakdown Voltage Masatoshi KOBAYASHI, Toshiro AKINO, Kenji NISHI, Kohsei TAKEHARA, T. Goji ETOH, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | We have been developing a ultra-high-speed camera by an in-situ storage image sensor (ISIS) with slanted linear CCD storage capturing 100 to 150 consecutive images at a frame rate of 100 Mfps. The CCD chip of this camera has a 8V maximum voltage supply source and a 5-nF maximum load capacitance per CCD clock. The goal of this study is to design a prototype power supply chip generating the clock, based on a 1.2-μmCMOS/SOI process having breakdown voltages of almost 32V. At first, we fit a set of LEVEL2 model parameters into the measured MOSFET current-voltage characteristics for a bulk type 1.2-μmCMOS process, and then only modify the substrate doping from a non-uniform diffusion profile with a channel doping to the uniform diffusion profile of the same channel doping along the direction of rather deep SOI substrate. As we try to make the substrate terminal to be non-floating and design a compact layout in order to reduce the resistance value of substrate interconnection, we optimize the size of unified-CBiCMOS buffer circuit for a high speed and low energy operation of lateral npn-and pnp-BJTs. Circuit simulation using 1.2-μm LEVEL-2 model parameters for the MOSFETs and a current gain of β_F=100 for the BJTs reduced the delay time of the unified-CBiCMOS buffer circuit by approximately 1/10 and slightly increased the energy of that by 103%, compared to that for an equivalent two-stage CMOS inverter circuit designed on the basis of logical effort for driving a load capacitance of 5-nF at V_ |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Slanted linear CCD storage / ISIS / CMOS/SOI / Lateral unified-CBiCMOS |
| Paper # | CAS2008-15,VLD2008-28,SIP2008-49 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2008/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Power Supply Chip for CCD in Ultra-High-Speed Camera Based on 1.2-μmCMOS/SOI Process with High Breakdown Voltage |
| Sub Title (in English) | |
| Keyword(1) | Slanted linear CCD storage |
| Keyword(2) | ISIS |
| Keyword(3) | CMOS/SOI |
| Keyword(4) | Lateral unified-CBiCMOS |
| 1st Author's Name | Masatoshi KOBAYASHI |
| 1st Author's Affiliation | School of Biology-Oriented Science and Technology, Kinki University() |
| 2nd Author's Name | Toshiro AKINO |
| 2nd Author's Affiliation | School of Biology-Oriented Science and Technology, Kinki University |
| 3rd Author's Name | Kenji NISHI |
| 3rd Author's Affiliation | Kinki University Technology College |
| 4th Author's Name | Kohsei TAKEHARA |
| 4th Author's Affiliation | School of Science and Engineering, Kinki University |
| 5th Author's Name | T. Goji ETOH |
| 5th Author's Affiliation | School of Science and Engineering, Kinki University |
| Date | 2008-06-26 |
| Paper # | CAS2008-15,VLD2008-28,SIP2008-49 |
| Volume (vol) | vol.108 |
| Number (no) | 104 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |