Presentation 2008-06-26
A study for performance modeling of circuits using MTCMOS power gating
Yusuke HIKOSAKA, Yuichiro TACHIKAWA, Junki MIYAJIMA, Masahiro FUKUI,
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Abstract(in English) In the processes before the 90nm generation, most of the power is consumed by the dynamic power which is consumed by the charge and discharge of the load capacitance. Accompanying with the progress of process technologies, the static power which is consumed by the leak current of transistors tends to increase. Specifically, it is expected that the leak current reaches from 50% to 70% when the process technology is smaller than 65nm. Therefore, the MTCMOS is one of important techniques to reduce the leak current. We propose a performance modeling of MTCMOS in this paper.
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Keyword(in English) MTCMOS / leak model / rush current / wake up time
Paper # CAS2008-13,VLD2008-26,SIP2008-47
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Committee CAS
Conference Date 2008/6/19(1days)
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Registration To Circuits and Systems (CAS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A study for performance modeling of circuits using MTCMOS power gating
Sub Title (in English)
Keyword(1) MTCMOS
Keyword(2) leak model
Keyword(3) rush current
Keyword(4) wake up time
1st Author's Name Yusuke HIKOSAKA
1st Author's Affiliation Graduate School Science and Engineering, Ritsumeikan University()
2nd Author's Name Yuichiro TACHIKAWA
2nd Author's Affiliation Graduate School Science and Engineering, Ritsumeikan University
3rd Author's Name Junki MIYAJIMA
3rd Author's Affiliation Dept. of VLSI system design, Ritsumeikan University
4th Author's Name Masahiro FUKUI
4th Author's Affiliation Dept. of VLSI system design, Ritsumeikan University
Date 2008-06-26
Paper # CAS2008-13,VLD2008-26,SIP2008-47
Volume (vol) vol.108
Number (no) 104
Page pp.pp.-
#Pages 6
Date of Issue