| Presentation | 2008-06-26 Evaluation of Dynamically Reconfigurable Processor in Implementing Sequential Execution of Image Processing Ryosuke WATANABE, Koki ABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, image applications are frequently executed using mobile devises, where executions with high speed at low cost are demanded. Typically, in image applications, procedures with high complexity are executed sequentially. In this study, we conducted an experiment to execute such an image application by a dynamically reconfigurable processor (DRP) and compared the processing speed with general purpose processors. We took a sequential application of median and Laplacian filters as an example. Results revealed that a DRP implementation executes 70 and 45 times faster than Celeron and Core2Duo processors, respectively. We also discussed area, energy, and development costs when using DRP, and compared the costs with FPGA and ASIC. When implementing image applications consisting of serial procedures, DRP is effective when the procedures are complex and available resources are limited. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable Processor / Image Processing / Processing Speed / Development Cost |
| Paper # | CAS2008-11,VLD2008-24,SIP2008-45 |
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| Conference Information | |
| Committee | CAS |
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| Conference Date | 2008/6/19(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Circuits and Systems (CAS) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Evaluation of Dynamically Reconfigurable Processor in Implementing Sequential Execution of Image Processing |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processor |
| Keyword(2) | Image Processing |
| Keyword(3) | Processing Speed |
| Keyword(4) | Development Cost |
| 1st Author's Name | Ryosuke WATANABE |
| 1st Author's Affiliation | Department of Computer Science, The University of Electro Communications() |
| 2nd Author's Name | Koki ABE |
| 2nd Author's Affiliation | Department of Computer Science, The University of Electro Communications |
| Date | 2008-06-26 |
| Paper # | CAS2008-11,VLD2008-24,SIP2008-45 |
| Volume (vol) | vol.108 |
| Number (no) | 104 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |