Presentation 2008-02-08
Current dissipation of Test pattern generators using ATPG vectors
Hidekazu Tsuchiya, Takaya Abe, Takeshi Asakawa,
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Abstract(in English) Recently, the operating speed of LSI is more fast and the scale of LSI is more larger. These induce increasing the dissipation power for testing. We evaluated about the fault coverage and the average current for K-division shift method.
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Keyword(in English) ATPG vector / Gated Clock / current dissipation / shift register
Paper # DC2007-80
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Committee DC
Conference Date 2008/2/1(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Current dissipation of Test pattern generators using ATPG vectors
Sub Title (in English)
Keyword(1) ATPG vector
Keyword(2) Gated Clock
Keyword(3) current dissipation
Keyword(4) shift register
1st Author's Name Hidekazu Tsuchiya
1st Author's Affiliation Graduate school of science and engineering, Tokai University()
2nd Author's Name Takaya Abe
2nd Author's Affiliation Graduate school of engineering, Tokai University
3rd Author's Name Takeshi Asakawa
3rd Author's Affiliation Graduate school of engineering, Tokai University
Date 2008-02-08
Paper # DC2007-80
Volume (vol) vol.107
Number (no) 482
Page pp.pp.-
#Pages 6
Date of Issue