Presentation 2008-02-08
Secure Scan Design Based on Balanced Structure
Muneo HASEGAWA, Michiko INOUE, Hideo FUJIWARA,
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Abstract(in English) In this paper, we propose a secure scan design which protects scan-based side channel attacks to the circuits containing secret information such as cryptographic circuits. The proposed method prevents the leakage of secret information by partial scan design based on the balanced structure and a data confusion mechanism while shifting scan chain. We also guarantee the testability of both the design under test and DFT circuitry, and therefore, realize both security and testability. Experiments for a RSA circuit shows the effectiveness of the proposed method.
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Keyword(in English) cryptographic hardware / scan-based DFT / balanced structure / security
Paper # DC2007-73
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Committee DC
Conference Date 2008/2/1(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Secure Scan Design Based on Balanced Structure
Sub Title (in English)
Keyword(1) cryptographic hardware
Keyword(2) scan-based DFT
Keyword(3) balanced structure
Keyword(4) security
1st Author's Name Muneo HASEGAWA
1st Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City()
2nd Author's Name Michiko INOUE
2nd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City
3rd Author's Name Hideo FUJIWARA
3rd Author's Affiliation Graduate School of Information Science, Nara Institute of Science and Technology Kansai Science City
Date 2008-02-08
Paper # DC2007-73
Volume (vol) vol.107
Number (no) 482
Page pp.pp.-
#Pages 6
Date of Issue