Presentation | 2008-02-08 Note on Test Power Reduction for Scan-Based Hybrid BIST Akifumi SUTO, Masayuki ARAI, Kazuhiko IWASAKI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In scan-based BIST, larger power dissipation at testing than normal operation may cause malfunctions during testing by power shortage or even damage on hardware by overheating. To reduce power consumption during testing, schemes such as the one considering don't-cares in the test patterns have been proposed. However, such schemes might reduce capability of defect detection. In this study we propose a test power reduction scheme based on BAST and Illinois scan, and evaluate them in respect to power consumption, test data volume, and defect detection capability by simulation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | BIST / BAST / low power test / n-detection test |
Paper # | DC2007-72 |
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Committee | DC |
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Conference Date | 2008/2/1(1days) |
Place (in Japanese) | (See Japanese page) |
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Topics (in Japanese) | (See Japanese page) |
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Registration To | Dependable Computing (DC) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Note on Test Power Reduction for Scan-Based Hybrid BIST |
Sub Title (in English) | |
Keyword(1) | BIST |
Keyword(2) | BAST |
Keyword(3) | low power test |
Keyword(4) | n-detection test |
1st Author's Name | Akifumi SUTO |
1st Author's Affiliation | Graduate School of System Design, Tokyo Metropolitan University() |
2nd Author's Name | Masayuki ARAI |
2nd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
3rd Author's Name | Kazuhiko IWASAKI |
3rd Author's Affiliation | Faculty of System Design, Tokyo Metropolitan University |
Date | 2008-02-08 |
Paper # | DC2007-72 |
Volume (vol) | vol.107 |
Number (no) | 482 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |