| Presentation | 2008-02-08 A Test Generation for Full Scan Circuit Using Multi Cycle Capture Test Yusho OMORI, Hiroshi OGAWA, Toshinori HOSOKAWA, Masayoshi YOSHIMURA, Kouji YAMAZAKI, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Currently, scan testing is one of the most popular test methods for VLSIs. In this testing, only information of the circuit structure is used, the circuit might be transferred to invalid state by the shift operation and it test. Therefore, it is considered that the scan testing is over testing. The occurrence of the yield loss and an increase in the test length are enumerated as an evil of the over testing. In this paper, a k-cycle capture test is proposed to detect faults by sequential operations in scan testing. Moreover, a k-cycle capture stuck-at fault test generation is proposed. Because k cycle sequential operation is performed in order to detect a fault in k-cycle capture test, it is considered that the probability that a state transfers to invalid state is low. In addition, it experiments to the ISCAS'89 bench mark circuit to show the effectiveness of the proposal technique. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Over testing / Sequential circuit test generation / k-cycle capture test / k-cycle capture stuck-at fault test generation |
| Paper # | DC2007-70 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2008/2/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Test Generation for Full Scan Circuit Using Multi Cycle Capture Test |
| Sub Title (in English) | |
| Keyword(1) | Over testing |
| Keyword(2) | Sequential circuit test generation |
| Keyword(3) | k-cycle capture test |
| Keyword(4) | k-cycle capture stuck-at fault test generation |
| 1st Author's Name | Yusho OMORI |
| 1st Author's Affiliation | Graduate School of Industrial Technology, Nihon University() |
| 2nd Author's Name | Hiroshi OGAWA |
| 2nd Author's Affiliation | College of Industrial Technology, Nihon University |
| 3rd Author's Name | Toshinori HOSOKAWA |
| 3rd Author's Affiliation | College of Industrial Technology, Nihon University |
| 4th Author's Name | Masayoshi YOSHIMURA |
| 4th Author's Affiliation | Graduate School of Infomation Science and Electrical Engineering, Kyushu University |
| 5th Author's Name | Kouji YAMAZAKI |
| 5th Author's Affiliation | School of Information and Communication, Meiji University |
| Date | 2008-02-08 |
| Paper # | DC2007-70 |
| Volume (vol) | vol.107 |
| Number (no) | 482 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |