Presentation 2008-02-08
Diagnostic Test Generation for Transition Faults
Takashi AIKYO, Yoshinobu HIGAMI, Hiroshi TAKAHASHI, Toru KIKKAWA, Yuzo TAKAMATSU,
PDF Download Page PDF download Page Link
Abstract(in Japanese) (See Japanese page)
Abstract(in English) In modern high-speed LSIs, defects that cause timing failure occur often, and thus their detection and diagnosis are getting crucial. In order to reduce candidate faults in fault diagnosis, the quality of diagnostic test patterns must be made high. In this research, we propose a test generation method for diagnosis of transition faults by using stuck-at test generation tool. First, we apply test patterns generated for detection of transition faults and obtain fault pairs that are not distinguished by these test patterns. In order to generate test patterns for distinguishing those indistinguished pairs, we add some logic to the original circuit and use a stuck-at test generation tool. This modified circuit is used during only the test generation process, and thus the method is different from a design-for-testability method. Moreover we identify indistinguishable fault pairs by circuit structure analysis. Experimental results for ISCAS benchmark circuits demonstrate the effectiveness of the proposed method.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) diagnostic tests / test generation / transition faults / delay faults / distinguishability
Paper # DC2007-69
Date of Issue

Conference Information
Committee DC
Conference Date 2008/2/1(1days)
Place (in Japanese) (See Japanese page)
Place (in English)
Topics (in Japanese) (See Japanese page)
Topics (in English)
Chair
Vice Chair
Secretary
Assistant

Paper Information
Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Diagnostic Test Generation for Transition Faults
Sub Title (in English)
Keyword(1) diagnostic tests
Keyword(2) test generation
Keyword(3) transition faults
Keyword(4) delay faults
Keyword(5) distinguishability
1st Author's Name Takashi AIKYO
1st Author's Affiliation Graduate School of Science and Engineering, Ehime University:Semiconductor Technology Academic Research Center()
2nd Author's Name Yoshinobu HIGAMI
2nd Author's Affiliation Graduate School of Science and Engineering, Ehime University
3rd Author's Name Hiroshi TAKAHASHI
3rd Author's Affiliation Graduate School of Science and Engineering, Ehime University
4th Author's Name Toru KIKKAWA
4th Author's Affiliation Graduate School of Science and Engineering, Ehime University
5th Author's Name Yuzo TAKAMATSU
5th Author's Affiliation Graduate School of Science and Engineering, Ehime University
Date 2008-02-08
Paper # DC2007-69
Volume (vol) vol.107
Number (no) 482
Page pp.pp.-
#Pages 6
Date of Issue