| Presentation | 2008-02-08 ESD/Latch up Failure Analysis of CMOS LSI : Failure Mode Analysis with Actual Data Hideo KOHINATA, Masayuki ARAI, Satoshi FUKUMOTO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | As the CMOS LSI advances, ESD/Latch-up problem is becoming more serious problem as a weakness of CMOS LSI structure. For the first step of our research, we analyze ESD/Latch-up fault with actual measurement data in order to cope with this problem. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | CMOS / Latch-up / ESD |
| Paper # | DC2007-67 |
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| Committee | DC |
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| Conference Date | 2008/2/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | ESD/Latch up Failure Analysis of CMOS LSI : Failure Mode Analysis with Actual Data |
| Sub Title (in English) | |
| Keyword(1) | CMOS |
| Keyword(2) | Latch-up |
| Keyword(3) | ESD |
| 1st Author's Name | Hideo KOHINATA |
| 1st Author's Affiliation | Tokyo Metropolitan University() |
| 2nd Author's Name | Masayuki ARAI |
| 2nd Author's Affiliation | Tokyo Metropolitan University |
| 3rd Author's Name | Satoshi FUKUMOTO |
| 3rd Author's Affiliation | Tokyo Metropolitan University |
| Date | 2008-02-08 |
| Paper # | DC2007-67 |
| Volume (vol) | vol.107 |
| Number (no) | 482 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |