Presentation | 2008-03-13 An Architecture of Dynamically Reconfigurable Systolic Array Toshiyuki ISHIMURA, Akinori KANASIGI, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | The Dynamically Reconfigurable Device which has high-speed performance of ASIC, flexibility of FPGA and high area efficiency is paid to attention recently. In this paper, we propose an element-block (DRSAB) which allows dynamic reconfiguration of systolic array. The array is constructed with simple PEs operating matrix calculation, and it is adapted to different size problems. In addition, the array can manage parallel processing by partially reconstructing the computing resources. The effectiveness of proposed DRSAB is confirmed with simulation. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Reconfigurable / Systolic Array / Processing Element / Digital signal processing |
Paper # | SIS2007-70 |
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Committee | SIS |
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Conference Date | 2008/3/6(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Smart Info-Media Systems (SIS) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | An Architecture of Dynamically Reconfigurable Systolic Array |
Sub Title (in English) | |
Keyword(1) | Reconfigurable |
Keyword(2) | Systolic Array |
Keyword(3) | Processing Element |
Keyword(4) | Digital signal processing |
1st Author's Name | Toshiyuki ISHIMURA |
1st Author's Affiliation | Graduate School of Engineering Tokyo Denki University() |
2nd Author's Name | Akinori KANASIGI |
2nd Author's Affiliation | Graduate School of Engineering Tokyo Denki University |
Date | 2008-03-13 |
Paper # | SIS2007-70 |
Volume (vol) | vol.107 |
Number (no) | 547 |
Page | pp.pp.- |
#Pages | 6 |
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