Presentation 2008-03-07
Code Optimization Method for Bypass Network Architecture by Evaluation of DFG
Toshihiro SHOJI, Jin TIAN, Takefumi MIYOSHI, Nobuhiko SUGINO,
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Abstract(in English) For a bypass interconnected processor architecture, a heuristic code optimization method is proposed. In total power consumption of a processor, power consumption at register access account for relatively higher percentage. For reducing this rate, there have been proposed a bypass interconnected architecture, which can replace register accesses by data forwarding latch accesses. In order to use bypass effectively, however, computational order of instruction codes should be rearranged. In this article, data dependencies in a given program is analyzed by the corresponding data flow graph, and a novel code rescheduling method is proposed. The proposed method is applied to an example program, and comparison of the resultant code with codes derived by the existing code optimization method based on computational order exchange, shows its effectiveness.
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Keyword(in English) Scheduling / Low-power / Bypass Network Architecture
Paper # CAS2007-139,SIP2007-214,CS2007-104
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Committee CS
Conference Date 2008/2/29(1days)
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Registration To Communication Systems (CS)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Code Optimization Method for Bypass Network Architecture by Evaluation of DFG
Sub Title (in English)
Keyword(1) Scheduling
Keyword(2) Low-power
Keyword(3) Bypass Network Architecture
1st Author's Name Toshihiro SHOJI
1st Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology()
2nd Author's Name Jin TIAN
2nd Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
3rd Author's Name Takefumi MIYOSHI
3rd Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
4th Author's Name Nobuhiko SUGINO
4th Author's Affiliation Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
Date 2008-03-07
Paper # CAS2007-139,SIP2007-214,CS2007-104
Volume (vol) vol.107
Number (no) 531
Page pp.pp.-
#Pages 4
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