| Presentation | 2008-05-23 Design and Implement Viterbi Decoder For Multi Constraint Length Using Reconfigurable Processor Yuken Kishimoto, Shinichiro Haruyama, Masao Nakagawa, Hideharu Amano, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | When Viterbi decoder is implemented with hard-wired logic, in order to adapt various decode conditions by changing the constraint length or decode precisions, dedicated hardware circuits for each condition are required and switched resulting extra cost and consuming power. Although this redundant hardware can be omitted by replacing the hardwired logic on FPGA (Field Programmable Gate Array), the time for loading configuration data often takes milliseconds and causes too long system stall. In this paper, we implemented the Viterbi algorithms whose constraint length are from 3 to 5 on Dynamic Reconfigurable Processor DAPDNA-II and replaced them according to the requirement. A certain threshold of BER is set for a fixed SNR and the Viterbi decoder with multiple constraint lengths is simulated. In the result of evaluation, when the at least 4.50Mbps throughput is ensured even with frequent reconfiguration was performed, the power consumption is reduced by 30%-80% compared with the case when a constraint length of the best performance is only utilized. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Reconfigurable Processor / Viterbi Decode / Software-Defined Radio |
| Paper # | RECONF2008-22 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/5/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design and Implement Viterbi Decoder For Multi Constraint Length Using Reconfigurable Processor |
| Sub Title (in English) | |
| Keyword(1) | Reconfigurable Processor |
| Keyword(2) | Viterbi Decode |
| Keyword(3) | Software-Defined Radio |
| 1st Author's Name | Yuken Kishimoto |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Shinichiro Haruyama |
| 2nd Author's Affiliation | Graduate School of System Design and Management, Keio University |
| 3rd Author's Name | Masao Nakagawa |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 4th Author's Name | Hideharu Amano |
| 4th Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2008-05-23 |
| Paper # | RECONF2008-22 |
| Volume (vol) | vol.108 |
| Number (no) | 48 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |