| Presentation | 2008-05-23 Designing And Evaluating Dynamically Reconfigurable Processor With Power Gating Technique Yoshiki SAITO, Tomoaki SHIRAI, Takuro NAKAMURA, Takashi NISHIMURA, Yohei HASEGAWA, Satoshi TSUTSUMI, Toshihiro KASHIMA, Mitsutaka NAKATA, Seidai TAKEDA, Kimiyoshi USAMI, Hideharu AMANO, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | A dynamically recofigurable processor achieves high performance making the best use of high degree of parallelism with its Processing Elements (PEs). However, while an application is running, not all PEs can be used for computation. Recently, the ratio of leakage power is increasing, due to the progressing process rule. Since even unused PEs consume the leakage power, it may shorten the battery driving time for mobile devices. Here, to alleviate this problem, we propose a dynamically reconfigurable architecture with power gating technique, MuCCRA2.32b-PG. By using the fine grained power gating technique, the power of unused PEs or units is cut off, if the sleeping time is more than the break-even point. As a result, 4.91% of area overhead came out, due to inserting sleep transistors and isolation cells. When the sleep signal was controlled for each PEs, 45% of leakage power was cut down at the maximum. during the execution of an application. On the other hand, when the signal was controlled for each units inside PEs, 48% of leakage power was reduced. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Dynamically Reconfigurable Processors / Fine Grained Power Gating / Leakage Power / Break Even Point |
| Paper # | RECONF2008-10 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/5/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Designing And Evaluating Dynamically Reconfigurable Processor With Power Gating Technique |
| Sub Title (in English) | |
| Keyword(1) | Dynamically Reconfigurable Processors |
| Keyword(2) | Fine Grained Power Gating |
| Keyword(3) | Leakage Power |
| Keyword(4) | Break Even Point |
| 1st Author's Name | Yoshiki SAITO |
| 1st Author's Affiliation | Faculty of Science and Technology, Keio University() |
| 2nd Author's Name | Tomoaki SHIRAI |
| 2nd Author's Affiliation | Faculty of Technology, Shibaura Institute of Technology |
| 3rd Author's Name | Takuro NAKAMURA |
| 3rd Author's Affiliation | Faculty of Science and Technology, Keio University |
| 4th Author's Name | Takashi NISHIMURA |
| 4th Author's Affiliation | Faculty of Science and Technology, Keio University |
| 5th Author's Name | Yohei HASEGAWA |
| 5th Author's Affiliation | Faculty of Science and Technology, Keio University |
| 6th Author's Name | Satoshi TSUTSUMI |
| 6th Author's Affiliation | Faculty of Science and Technology, Keio University |
| 7th Author's Name | Toshihiro KASHIMA |
| 7th Author's Affiliation | Faculty of Technology, Shibaura Institute of Technology |
| 8th Author's Name | Mitsutaka NAKATA |
| 8th Author's Affiliation | Faculty of Technology, Shibaura Institute of Technology |
| 9th Author's Name | Seidai TAKEDA |
| 9th Author's Affiliation | Faculty of Technology, Shibaura Institute of Technology |
| 10th Author's Name | Kimiyoshi USAMI |
| 10th Author's Affiliation | Faculty of Technology, Shibaura Institute of Technology |
| 11th Author's Name | Hideharu AMANO |
| 11th Author's Affiliation | Faculty of Science and Technology, Keio University |
| Date | 2008-05-23 |
| Paper # | RECONF2008-10 |
| Volume (vol) | vol.108 |
| Number (no) | 48 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |