| Presentation | 2008-05-22 A Novel Cluster Structure for Variable Grain Logic Cell Kazuki INOUE, Kazunori MATSUYAMA, Yoshiaki SATOU, Masahiro KOGA, Motoki AMAGASAKI, Masahiro IIDA, Toshinori SUEYOSHI, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic logic cell architecture. In general, each architecture has its own advantages; therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In this study, we propose a variable grain logic cell (VGLC) architecture. Its key feature is the variable granularity that is a trade-off between the coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. In this paper, we propose a cluster structure for the VGLC. In the proposed cluster structure, we cluster three VGLCs and provide a local routing block to interconnect them to improve the circuit speed. In order to evaluate the proposed cluster structure, we implemented adder circuits and multipliers. As a result, carry select adder was the suitable adder circuit for the proposed cluster structure. In the case of multiplier, we need to select the suitable arithmetic algorithm according to the trade-off between delay and area. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | reconfigurable logic device / coarse-grain / fine-grain / cluster / arithmetic operation circuit |
| Paper # | RECONF2008-8 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/5/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Novel Cluster Structure for Variable Grain Logic Cell |
| Sub Title (in English) | |
| Keyword(1) | reconfigurable logic device |
| Keyword(2) | coarse-grain |
| Keyword(3) | fine-grain |
| Keyword(4) | cluster |
| Keyword(5) | arithmetic operation circuit |
| 1st Author's Name | Kazuki INOUE |
| 1st Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University() |
| 2nd Author's Name | Kazunori MATSUYAMA |
| 2nd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 3rd Author's Name | Yoshiaki SATOU |
| 3rd Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 4th Author's Name | Masahiro KOGA |
| 4th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 5th Author's Name | Motoki AMAGASAKI |
| 5th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 6th Author's Name | Masahiro IIDA |
| 6th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| 7th Author's Name | Toshinori SUEYOSHI |
| 7th Author's Affiliation | Graduate School of Sience and Technology, Kumamoto University |
| Date | 2008-05-22 |
| Paper # | RECONF2008-8 |
| Volume (vol) | vol.108 |
| Number (no) | 48 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |