講演名 | 2008-05-22 A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs , |
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抄録(和) | |
抄録(英) | The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization, In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing that is a representative deadlock-free routing on irregular topology. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation. |
キーワード(和) | |
キーワード(英) | Network-on-Chip / Link / FPGA / Topology / Routing |
資料番号 | RECONF2008-7 |
発行日 |
研究会情報 | |
研究会 | RECONF |
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開催期間 | 2008/5/15(から1日開催) |
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講演論文情報詳細 | |
申込み研究会 | Reconfigurable Systems (RECONF) |
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本文の言語 | ENG |
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サブタイトル(和) | |
タイトル(英) | A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs |
サブタイトル(和) | |
キーワード(1)(和/英) | / Network-on-Chip |
第 1 著者 氏名(和/英) | / Daihan WANG |
第 1 著者 所属(和/英) | Department of Information and Computer Science, Keio University:JST |
発表年月日 | 2008-05-22 |
資料番号 | RECONF2008-7 |
巻番号(vol) | vol.108 |
号番号(no) | 48 |
ページ範囲 | pp.- |
ページ数 | 6 |
発行日 |