| Presentation | 2008-05-22 A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs Daihan WANG, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization, In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost with enough performance being kept. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing that is a representative deadlock-free routing on irregular topology. In the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Network-on-Chip / Link / FPGA / Topology / Routing |
| Paper # | RECONF2008-7 |
| Date of Issue |
| Conference Information | |
| Committee | RECONF |
|---|---|
| Conference Date | 2008/5/15(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
|---|---|
| Language | ENG |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Link Removal Methodology for Application-Specific Networks-on-chip on FPGAs |
| Sub Title (in English) | |
| Keyword(1) | Network-on-Chip |
| Keyword(2) | Link |
| Keyword(3) | FPGA |
| Keyword(4) | Topology |
| Keyword(5) | Routing |
| 1st Author's Name | Daihan WANG |
| 1st Author's Affiliation | Department of Information and Computer Science, Keio University:JST() |
| 2nd Author's Name | Hiroki MATSUTANI |
| 2nd Author's Affiliation | Department of Information and Computer Science, Keio University |
| 3rd Author's Name | Michihiro KOIBUCHI |
| 3rd Author's Affiliation | National Institute of Informatics JST |
| 4th Author's Name | Hideharu AMANO |
| 4th Author's Affiliation | Department of Information and Computer Science, Keio University |
| Date | 2008-05-22 |
| Paper # | RECONF2008-7 |
| Volume (vol) | vol.108 |
| Number (no) | 48 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |