Presentation | 2008-05-22 An Implementation of High Precision Floating-point Operation Units on FPGA Naohito NAKASATO, Tadashi ISHIKAWA, |
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Abstract(in English) | Kinds of numerical application programs require high-precision (better than double-precision) floating-point (FP) operations. An example of such applications is a numerical evaluation of Feynmann loop integrals. To evaluate those integrals with a desired accuracy on conventional CPUs, one utilize emulation techniques using double-precision operations or 64-bit integer operations. However, a perfomance penalty of emulation techniques is as large as 4-5% of DP operations. To tackle those problems, we are currently working on implementation of quadruple-precision floating-point operation units on a FPGA device. We report a current status of our project and propose a computation unit that is capable of high-precision numerical integration. |
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Paper # | RECONF2008-2 |
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Committee | RECONF |
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Conference Date | 2008/5/15(1days) |
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Registration To | Reconfigurable Systems (RECONF) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
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Title (in English) | An Implementation of High Precision Floating-point Operation Units on FPGA |
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1st Author's Name | Naohito NAKASATO |
1st Author's Affiliation | University of Aizu() |
2nd Author's Name | Tadashi ISHIKAWA |
2nd Author's Affiliation | High Energy Accelerator Research Organization, KEK |
Date | 2008-05-22 |
Paper # | RECONF2008-2 |
Volume (vol) | vol.108 |
Number (no) | 48 |
Page | pp.pp.- |
#Pages | 5 |
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