| Presentation | 2008-05-09 On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints Makoto SUGIHARA, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional design flow, while chip area, performance, and power consumption have been. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and SEU vulnerability constraints. We build an MIP model for minimizing chip area of a heterogeneous multiprocessor system under the constraints. Experimental results show that our design paradigm have achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | SEU / Soft Error / Real-Time / SEU Vulnerability / Heterogeneous Multiprocessor |
| Paper # | VLD2008-13 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/5/2(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | On Synthesizing a Heterogeneous Multiprocessor System under Real-Time and SEU Vulnerability Constraints |
| Sub Title (in English) | |
| Keyword(1) | SEU |
| Keyword(2) | Soft Error |
| Keyword(3) | Real-Time |
| Keyword(4) | SEU Vulnerability |
| Keyword(5) | Heterogeneous Multiprocessor |
| 1st Author's Name | Makoto SUGIHARA |
| 1st Author's Affiliation | Toyohashi University of Technology:Japan Science and Technology Agency, CREST() |
| Date | 2008-05-09 |
| Paper # | VLD2008-13 |
| Volume (vol) | vol.108 |
| Number (no) | 23 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |