Presentation | 2008-05-08 Improvement Technique of Binding for Multiplexer Reduction Sho KODAMA, Yusuke MATSUNAGA, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | In Behavioral Synthesis for resource shared architecture, multiplexers are inserted between registers and functional units as a result of binding if necessary. Multiplexer optimization in binding is important for performance and area of synthesized circuit. In this paper, we propose an improvement technique of binding to reduce total amount of multiplexer ports. In our approach, starting point is initial register binding and initial functional unit binding. Both functional unit binding and register binding are modified by local improvements based on taboo search iteratively. Experimental results show that our approach is able to reduce total amount of multiplexer ports by 30% on an average compared to a traditional binding algorithm. Computation time of our approach is several seconds to a few minutes. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Behavioral Synthesis / Binding / EDA |
Paper # | VLD2008-4 |
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Committee | VLD |
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Conference Date | 2008/5/1(1days) |
Place (in Japanese) | (See Japanese page) |
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Paper Information | |
Registration To | VLSI Design Technologies (VLD) |
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Language | JPN |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Improvement Technique of Binding for Multiplexer Reduction |
Sub Title (in English) | |
Keyword(1) | Behavioral Synthesis |
Keyword(2) | Binding |
Keyword(3) | EDA |
1st Author's Name | Sho KODAMA |
1st Author's Affiliation | Graduate Schoool of Information Science and Electrical Engineering, Kyushu University() |
2nd Author's Name | Yusuke MATSUNAGA |
2nd Author's Affiliation | Faculty Schoool of Information Science and Electrical Engineering, Kyushu University |
Date | 2008-05-08 |
Paper # | VLD2008-4 |
Volume (vol) | vol.108 |
Number (no) | 22 |
Page | pp.pp.- |
#Pages | 6 |
Date of Issue |