| Presentation | 2008-05-08 HW/SW Co-verification Method using FPGAs Yuichi Nakamura, Kouhei Hosokawa, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In this paper, we describe HW/SW co-verification method using FPGAs, which can be applied for the software debugging on system LSI. Recently, the complexity of software on system LSIs is going to increase, according to increasing of the scale of system LSI on the development for digital TV and mobile phones. Thus, both the hardware design and verification and the software design and verification are very important, since the software is running at the optimized and customized hardware for applications. In addition the verification time of system LSI is much larger than the design time. Then, HW/SW co-verification system is needed. We proposed the HW/SW co-verification system using FPGA and contributed the reduction of the time and cost of the system LSI development. This system can be handled software debugging like as "Break" and "Step" in spite of FPGA based emulator and can be archived the detailed verification before fabrication, although the conventional system can not be applied for the software debugging. We describe the detail system specification and the examples of the proposed systems. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | HW/SW Co-verification / Debugging / FPGA |
| Paper # | VLD2008-1 |
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| Conference Information | |
| Committee | VLD |
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| Conference Date | 2008/5/1(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | VLSI Design Technologies (VLD) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | HW/SW Co-verification Method using FPGAs |
| Sub Title (in English) | |
| Keyword(1) | HW/SW Co-verification |
| Keyword(2) | Debugging |
| Keyword(3) | FPGA |
| 1st Author's Name | Yuichi Nakamura |
| 1st Author's Affiliation | System IP Core Laboratories, NEC Corp.() |
| 2nd Author's Name | Kouhei Hosokawa |
| 2nd Author's Affiliation | System IP Core Laboratories, NEC Corp. |
| Date | 2008-05-08 |
| Paper # | VLD2008-1 |
| Volume (vol) | vol.108 |
| Number (no) | 22 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |