| Presentation | 2008-04-23 An approach to tolerating delay faults based on asynchronous circuits Tomohiro YONEDA, Masashi IMAI, Atsushi MATSUMOTO, Takahiro HANYU, Yuichi NAKAMURA, |
|---|---|
| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recent advances in semiconductor process technologies cause new types of faults, which should be handled in order to obtain large and dependable VLSI systems. This report focuses on a type of faults that are caused by the stress during the operation and degrade performance of the circuit components. We analyze the influence of those delay faults in a data-flow level of bardware accelerators showing that asynchronous circuits are more robust than synchronous circuits with respect to such delay faults, and propose an approach to tolerating them using asynchronous circuit technologies and operational unit reallocation. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Delay faults / Asynchronous circuits / Operational unit reallocation |
| Paper # | CPSY2008-10,DC2008-10 |
| Date of Issue |
| Conference Information | |
| Committee | DC |
|---|---|
| Conference Date | 2008/4/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Chair | |
| Vice Chair | |
| Secretary | |
| Assistant | |
| Paper Information | |
| Registration To | Dependable Computing (DC) |
|---|---|
| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An approach to tolerating delay faults based on asynchronous circuits |
| Sub Title (in English) | |
| Keyword(1) | Delay faults |
| Keyword(2) | Asynchronous circuits |
| Keyword(3) | Operational unit reallocation |
| 1st Author's Name | Tomohiro YONEDA |
| 1st Author's Affiliation | National Institute of Informatics() |
| 2nd Author's Name | Masashi IMAI |
| 2nd Author's Affiliation | Komaba Open Labo., The University of Tokyo |
| 3rd Author's Name | Atsushi MATSUMOTO |
| 3rd Author's Affiliation | Research Inst. of Electrical Comm., Tohoku Univ. |
| 4th Author's Name | Takahiro HANYU |
| 4th Author's Affiliation | Research Inst. of Electrical Comm., Tohoku Univ. |
| 5th Author's Name | Yuichi NAKAMURA |
| 5th Author's Affiliation | System IP Core Research Labos., NEC |
| Date | 2008-04-23 |
| Paper # | CPSY2008-10,DC2008-10 |
| Volume (vol) | vol.108 |
| Number (no) | 15 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |