| Presentation | 2008-04-23 Soft Error Hardened FF Capable of Detecting Wide Error Pulse Shuangyu RUAN, Kazuteru NAMBA, Hideo ITO, |
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| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | In the recent high-density and low-power VLSIs, occurrence of soft errors becomes significant problems. Recently, soft errors frequently occur on not only memory systems and latches but also combinational parts of logic circuits. Based on this standpoint, a construction of soft error tolerant FFs has been proposed. The construction is for dual module redundancy system and the FF consists of some master and slave latches and C-elements. In the FFs, soft error pulses occurring on combinational parts of logic circuits are correct5ed as long as the width of the pulses is narrow. However, soft error pulses having wide width are neither detected nor corrected in the FFs. This paper presents a construction of soft error tolerant FFs. The proposed FFs are also capable of detecting hard errors. This paper also presents scan FFs facilitating delay fault testing and soft error tolerant FFs for dual-rail logic circuit based on the proposed FFs. The evaluation shows that the area of the proposed FF is up to 66% larger than that of the conventional soft error tolerant FFs. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | soft error / hard error / C-Element / delay fault / dual-rail logic circuit |
| Paper # | CPSY2008-9,DC2008-9 |
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| Conference Information | |
| Committee | DC |
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| Conference Date | 2008/4/16(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Dependable Computing (DC) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Soft Error Hardened FF Capable of Detecting Wide Error Pulse |
| Sub Title (in English) | |
| Keyword(1) | soft error |
| Keyword(2) | hard error |
| Keyword(3) | C-Element |
| Keyword(4) | delay fault |
| Keyword(5) | dual-rail logic circuit |
| 1st Author's Name | Shuangyu RUAN |
| 1st Author's Affiliation | Graduate School of Advanced Integration Science, Chiba University() |
| 2nd Author's Name | Kazuteru NAMBA |
| 2nd Author's Affiliation | Graduate School of Advanced Integration Science, Chiba University |
| 3rd Author's Name | Hideo ITO |
| 3rd Author's Affiliation | Graduate School of Advanced Integration Science, Chiba University |
| Date | 2008-04-23 |
| Paper # | CPSY2008-9,DC2008-9 |
| Volume (vol) | vol.108 |
| Number (no) | 15 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |