Presentation 2008/3/20
A Functional Unit with Small Variety of Highly Reliable Cells and Its Evaluation
Kazunori SUZUKI, Takashi NAKADA, Masaki NAKANISHI, Shigeru YAMASHITA, Yasuhiko NAKASHIMA,
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Abstract(in English) Recently, the shrinking process causes growth of error rate. We have proposed new standard cells in which transistors are arranged regularly in order to reduce errors. These cells are composed of pairs of PMOS and NMOS. The proposed cells are more robust against transistor faults and can also detect them. In this paper, we propose and evaluate a functional unit that is composed of the proposed cells. The number of transistors in our proposed functional unit is comparable that by traditional cells. Moreover our proposed functional unit has better fault tolerance.
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Keyword(in English) transistor variation / fault detection / fault tolerantce
Paper # CPSY2007-108,DC2007-112
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Committee CPSY
Conference Date 2008/3/20(1days)
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Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) A Functional Unit with Small Variety of Highly Reliable Cells and Its Evaluation
Sub Title (in English)
Keyword(1) transistor variation
Keyword(2) fault detection
Keyword(3) fault tolerantce
1st Author's Name Kazunori SUZUKI
1st Author's Affiliation Nara Institute of Science and Technology()
2nd Author's Name Takashi NAKADA
2nd Author's Affiliation Nara Institute of Science and Technology
3rd Author's Name Masaki NAKANISHI
3rd Author's Affiliation Nara Institute of Science and Technology
4th Author's Name Shigeru YAMASHITA
4th Author's Affiliation Nara Institute of Science and Technology
5th Author's Name Yasuhiko NAKASHIMA
5th Author's Affiliation Nara Institute of Science and Technology
Date 2008/3/20
Paper # CPSY2007-108,DC2007-112
Volume (vol) vol.107
Number (no) 558
Page pp.pp.-
#Pages 6
Date of Issue