Presentation | 2008/3/20 Synthesis for Detection of Transient Faults Goerschwin FEY, Rolf DRECHSLER, |
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Abstract(in Japanese) | (See Japanese page) |
Abstract(in English) | Steadily shrinking feature sizes of circuits are the guarantee to keep up with Moore's law. But this also degrades the reliability of individual components continuously. Realizing correctly working circuits using unreliable components is a main objective for future design flows. In this work we present a technique to automatically synthesize robust circuits, i.e. circuits that are able to detect a transient fault. The BDD-based synthesis technique MuTaTe [1] is used to enable functional tests. Similar to the razor approach [2], these tests are performed in a time multiplexed scheme instead of adding redundant logic. As a result the area overhead in comparison to a non-robust circuit for the same function is often negligible. Experimental results for benchmark circuits are provided. |
Keyword(in Japanese) | (See Japanese page) |
Keyword(in English) | Synthesis / Robustness / Synthesis for Testability |
Paper # | CPSY2007-107,DC2007-111 |
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Committee | CPSY |
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Conference Date | 2008/3/20(1days) |
Place (in Japanese) | (See Japanese page) |
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Registration To | Computer Systems (CPSY) |
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Language | ENG |
Title (in Japanese) | (See Japanese page) |
Sub Title (in Japanese) | (See Japanese page) |
Title (in English) | Synthesis for Detection of Transient Faults |
Sub Title (in English) | |
Keyword(1) | Synthesis |
Keyword(2) | Robustness |
Keyword(3) | Synthesis for Testability |
1st Author's Name | Goerschwin FEY |
1st Author's Affiliation | Institute of Computer Science, University of Bremen:VLSI Design and Education Center, University of Tokyo() |
2nd Author's Name | Rolf DRECHSLER |
2nd Author's Affiliation | Institute of Computer Science, University of Bremen |
Date | 2008/3/20 |
Paper # | CPSY2007-107,DC2007-111 |
Volume (vol) | vol.107 |
Number (no) | 558 |
Page | pp.pp.- |
#Pages | 6 |
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