Presentation 2008/3/20
A technique of automatic input pattern generation for system-level design descriptions by concrete and symbolic simulations
Yoshihisa KOJIMA, Tasuku NISHIHARA, Takeshi MATSUMOTO, Masahiro FUJITA,
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Abstract(in English) As the VLSI systems grow larger and more complicated, it becomes more difficult to manually prepare the input patterns on simulation-based verification and debugging. In this research, we try to automatically generate the input patterns which cause the assertion failure, by exercising concrete and symbolic simulations simultaneously on the design descriptions in the extended system dependence graphs. Our goals are i) to promote to automate the input pattern generation process, ii) to activate the corner-cases and discover the bugs hard to find by random simulation, and iii) to achieve a better code coverage.
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Keyword(in English) symbolic simulation / concrete/symbolic-hybrid simulation / input pattern generation / verification / code coverage
Paper # CPSY2007-102,DC2007-106
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Committee CPSY
Conference Date 2008/3/20(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
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Title (in English) A technique of automatic input pattern generation for system-level design descriptions by concrete and symbolic simulations
Sub Title (in English)
Keyword(1) symbolic simulation
Keyword(2) concrete/symbolic-hybrid simulation
Keyword(3) input pattern generation
Keyword(4) verification
Keyword(5) code coverage
1st Author's Name Yoshihisa KOJIMA
1st Author's Affiliation Electronic Engineering, the University of Tokyo()
2nd Author's Name Tasuku NISHIHARA
2nd Author's Affiliation Electronic Engineering, the University of Tokyo
3rd Author's Name Takeshi MATSUMOTO
3rd Author's Affiliation Electronic Engineering, the University of Tokyo
4th Author's Name Masahiro FUJITA
4th Author's Affiliation VLSI Design and Education Center, the University of Tokyo
Date 2008/3/20
Paper # CPSY2007-102,DC2007-106
Volume (vol) vol.107
Number (no) 558
Page pp.pp.-
#Pages 6
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