| Presentation | 2008/3/20 An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA Masayuki HIROMOTO, Hiroyuki OCHI, Yukihiro NAKAMURA, |
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| PDF Download Page | PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Synchronous design methodology is widely used for today's digital circuits. However, it is difficult to reuse a highly-optimized synchronous module for a specific clock frequency to other systems with different global clocks, because logic depth between FFs should be tailored for the clock frequency. In this paper, we focus on asynchronous design, in which each module works at its best performance, and apply it to an IEEE754-standard single-precision floating-point divider. Our divider is ready to be built into a system with arbitrary clock frequency and achieves its peak performance and area- and power-efficiency. This paper also reports an implementation result and performance evaluation of the proposed divider on a Xilinx Virtex-4 FPGA. The evaluation results shows our divider achieves smaller area, lower power consumption, and higher throughput than the synchronous dividers. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | Arithmetic operation circuit / IP reusability / low power design / digit-recurrence divider |
| Paper # | CPSY2007-101,DC2007-105 |
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| Conference Information | |
| Committee | CPSY |
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| Conference Date | 2008/3/20(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Computer Systems (CPSY) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Asynchronous IEEE754-standard Single-precision Floating-point Divider for FPGA |
| Sub Title (in English) | |
| Keyword(1) | Arithmetic operation circuit |
| Keyword(2) | IP reusability |
| Keyword(3) | low power design |
| Keyword(4) | digit-recurrence divider |
| 1st Author's Name | Masayuki HIROMOTO |
| 1st Author's Affiliation | Dept. of Communications and Computer Eng., Graduate School of Informatics, Kyoto Univ.() |
| 2nd Author's Name | Hiroyuki OCHI |
| 2nd Author's Affiliation | Dept. of Communications and Computer Eng., Graduate School of Informatics, Kyoto Univ. |
| 3rd Author's Name | Yukihiro NAKAMURA |
| 3rd Author's Affiliation | Research Organization of Science and Engineering, Ritsumeikan Univ. |
| Date | 2008/3/20 |
| Paper # | CPSY2007-101,DC2007-105 |
| Volume (vol) | vol.107 |
| Number (no) | 558 |
| Page | pp.pp.- |
| #Pages | 6 |
| Date of Issue | |