Presentation 2008/3/20
On Evaluation Methods of nMOS Level Shifter Circuits
Makoto OTSU, Shingo TAKAHASHI, Shuji TSUKIYAMA, Masanori HASHIMOTO, Isao SHIRAKAWA,
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Abstract(in English) When the process technology or required specification is changed, we face a problem of finding the optimum circuit among various circuits with the same functionality. The problem is not easy to solve, since there exist many metrics to evaluate the circuits. This paper proposes a method to compare circuits with the use of a circuit optimizer and applies the method to nMOS level shifter circuits. The experimental results show that the method helps capturing the circuit features and devising a new level shifter.
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Keyword(in English) nMOS level shifter / driver circuit for LCD / circuit performance / evaluation method
Paper # CPSY2007-100,DC2007-104
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Committee CPSY
Conference Date 2008/3/20(1days)
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Paper Information
Registration To Computer Systems (CPSY)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) On Evaluation Methods of nMOS Level Shifter Circuits
Sub Title (in English)
Keyword(1) nMOS level shifter
Keyword(2) driver circuit for LCD
Keyword(3) circuit performance
Keyword(4) evaluation method
1st Author's Name Makoto OTSU
1st Author's Affiliation Graduate School of Science and Engineering, Chuo University()
2nd Author's Name Shingo TAKAHASHI
2nd Author's Affiliation Graduate School of Science and Engineering, Chuo University
3rd Author's Name Shuji TSUKIYAMA
3rd Author's Affiliation Graduate School of Science and Engineering, Chuo University
4th Author's Name Masanori HASHIMOTO
4th Author's Affiliation Graduate School of Information Science and Technology, Osaka University
5th Author's Name Isao SHIRAKAWA
5th Author's Affiliation Graduate School of Applied Informatics, University of Hyogo
Date 2008/3/20
Paper # CPSY2007-100,DC2007-104
Volume (vol) vol.107
Number (no) 558
Page pp.pp.-
#Pages 6
Date of Issue