Presentation	2008/3/20 A Hardware Acceleration for Semi-Formal Model Checking Satoshi MORISHITA, Hiroaki YOSHIDA, Masahiro FUJITA,
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Abstract(in English)	The verification becomes important now as the design becomes complex and large-scale. Model checking which is one of the most important verification has been held back by the state explosion problem, which is the problem that the number of states grows exponentially in the number of system components. So we propose an efficient model checking method in this paper. We have enhanced a semi-formal bounded model checking [8] by using a hardware accelerator and modified the codes to be easily implemented on a hardware. The experimental results with some examples show that the proposed method can execute model checking in short time.
Keyword(in Japanese)	(See Japanese page)
Keyword(in English)	Model Checking
Paper #	CPSY2007-99,DC2007-103
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Conference Information
Committee	CPSY
Conference Date	2008/3/20(1days)
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Paper Information
Registration To	Computer Systems (CPSY)
Language	JPN
Title (in Japanese)	(See Japanese page)
Sub Title (in Japanese)	(See Japanese page)
Title (in English)	A Hardware Acceleration for Semi-Formal Model Checking
Sub Title (in English)
Keyword(1)	Model Checking
1st Author's Name	Satoshi MORISHITA
1st Author's Affiliation	Department of Electronics Engineering, Faculty of Engineering, University of Tokyo()
2nd Author's Name	Hiroaki YOSHIDA
2nd Author's Affiliation	VLSI Design and Education Center, University of Tokyo
3rd Author's Name	Masahiro FUJITA
3rd Author's Affiliation	VLSI Design and Education Center, University of Tokyo
Date	2008/3/20
Paper #	CPSY2007-99,DC2007-103
Volume (vol)	vol.107
Number (no)	558
Page	pp.pp.-
#Pages	6
Date of Issue