Presentation 2008/3/20
Prioritized Non-Uniform Cache Architecture for Chip Multiprocessors
Nobuaki SAKAMOTO, Nobuyuki YAMASAKI,
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Abstract(in English) In recent years, high performance processors like Chip Multiprocessors (CMPs) have been required even in embedded real-time systems. The performance of CMPs often depends on the configuration of the last-level caches. The traditional Non-Uniform Cache Architecture (NUCA) can achive both short latency and high hit ratio by utilizing the migration of cache blocks. However, the exisiting migration policies for NUCA are based on the state of the cache blocks or the access frequency, and they may cause priority inversion problems in real-time systems. In order to solve the problem, we propose the migration policies based on the priority. In addition, we replace the blocks if they are predicted as dead blocks to improve the total performance.
Keyword(in Japanese) (See Japanese page)
Keyword(in English) Chip Multiprocessors / Non-Uniform Cache Architecure / Real-Time Systems
Paper # CPSY2007-81,DC2007-85
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Committee DC
Conference Date 2008/3/20(1days)
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Registration To Dependable Computing (DC)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Prioritized Non-Uniform Cache Architecture for Chip Multiprocessors
Sub Title (in English)
Keyword(1) Chip Multiprocessors
Keyword(2) Non-Uniform Cache Architecure
Keyword(3) Real-Time Systems
1st Author's Name Nobuaki SAKAMOTO
1st Author's Affiliation Graduate School of Science and Technology, Keio University()
2nd Author's Name Nobuyuki YAMASAKI
2nd Author's Affiliation Graduate School of Science and Technology, Keio University
Date 2008/3/20
Paper # CPSY2007-81,DC2007-85
Volume (vol) vol.107
Number (no) 559
Page pp.pp.-
#Pages 6
Date of Issue