Presentation 2008-01-17
An L1 Data Cache Optimization Algorithm for Application Processor Cores
Nobuaki TOJO, Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI,
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Abstract(in English) One major factor in improving the performance of embedded processors is the use of data and instruction caches. In this paper, we propose an L1 data cache optimization algorithm which selects a suitable cache configuration for a given embedded application. Our algorithm can have the area constraint by introducing CRMF (Configuration Reduction approach by the Miss Factor) and CRCB(Configuration Reduction approach by the Cache Behavior). Our algorithm finally selects best cache size, block size and associativity under the area constraint for a targeted application. We demonstrate the effectiveness of our algorithm by applying it to Mediabench.
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Keyword(in English) data cache / cache optimization / embedded system / processor core
Paper # VLD2007-131,CPSY2007-74,RECONF2007-77
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Committee RECONF
Conference Date 2008/1/10(1days)
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Registration To Reconfigurable Systems (RECONF)
Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) An L1 Data Cache Optimization Algorithm for Application Processor Cores
Sub Title (in English)
Keyword(1) data cache
Keyword(2) cache optimization
Keyword(3) embedded system
Keyword(4) processor core
1st Author's Name Nobuaki TOJO
1st Author's Affiliation Dept. of Computer Science and Engineering, Waseda University()
2nd Author's Name Nozomu TOGAWA
2nd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
3rd Author's Name Masao YANAGISAWA
3rd Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
4th Author's Name Tatsuo OHTSUKI
4th Author's Affiliation Dept. of Computer Science and Engineering, Waseda University
Date 2008-01-17
Paper # VLD2007-131,CPSY2007-74,RECONF2007-77
Volume (vol) vol.107
Number (no) 419
Page pp.pp.-
#Pages 6
Date of Issue