| Presentation | 2008-01-17 Analysis of retention time under continuous reconfiguration of a DORGA. Daisaku SETO, Minoru WATANABE, |
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| PDF Download Page |  PDF download Page Link |
| Abstract(in Japanese) | (See Japanese page) |
| Abstract(in English) | Recently, various fast reconfigurable devices have been developed. We have been developing a type of such fast reconfigurable devices, Optically Reconfigurable Gate Arrays (ORGAs) that can be reconfigured with optical components in a perfectly parallel. In such ORGAs, we have proposed a dynamic optically reconfigurable gate array (DORGA) architecture that uses photodiode as dynamic memory to store a configuration context, achieving large gates. However, it was concerned that when a certain circuit is programmed to a gate array and works on it, and the other configuration is applied into the different gate array area, the configuration of the other area may affect the working circuit and may reduce the retention time of the working circuit. So, the influence was investigated. This paper shows experimental results demonstrating that the DORGA architecture is effective under dynamic reconfigurations. |
| Keyword(in Japanese) | (See Japanese page) |
| Keyword(in English) | FPGAs / Optically Reconfigurable Gate Arrays / Optical bus / Holographic memories |
| Paper # | VLD2007-125,CPSY2007-68,RECONF2007-71 |
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| Conference Information | |
| Committee | RECONF |
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| Conference Date | 2008/1/10(1days) |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
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| Paper Information | |
| Registration To | Reconfigurable Systems (RECONF) |
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| Language | JPN |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis of retention time under continuous reconfiguration of a DORGA. |
| Sub Title (in English) | |
| Keyword(1) | FPGAs |
| Keyword(2) | Optically Reconfigurable Gate Arrays |
| Keyword(3) | Optical bus |
| Keyword(4) | Holographic memories |
| 1st Author's Name | Daisaku SETO |
| 1st Author's Affiliation | Faculty of Engineering, Shizuoka University() |
| 2nd Author's Name | Minoru WATANABE |
| 2nd Author's Affiliation | Faculty of Engineering, Shizuoka University |
| Date | 2008-01-17 |
| Paper # | VLD2007-125,CPSY2007-68,RECONF2007-71 |
| Volume (vol) | vol.107 |
| Number (no) | 419 |
| Page | pp.pp.- |
| #Pages | 5 |
| Date of Issue | |