Presentation 2008-01-17
Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation
Takahiro KAWAHARA, Shinobu MIWA, Hajime SHIMADA, Shin-ichiro MORI, Shinji TOMITA,
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Abstract(in English) We are developing the parallel volume rendering accelerator VisA. VisA communicates with one-way link over DVI-D which is usualy used as a display interface, so it achieves the fine grain pipeline system which integrates both image composition between nodes and image rendering inside a node. This paper describes the design concept of VisA and its preliminary implementation.
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Keyword(in English) Visualization / Volume Rendering / Parallel Processing / FPGA / Hardware Accelerator
Paper # VLD2007-122,CPSY2007-65,RECONF2007-68
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Committee RECONF
Conference Date 2008/1/10(1days)
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Language JPN
Title (in Japanese) (See Japanese page)
Sub Title (in Japanese) (See Japanese page)
Title (in English) Development of Parallel Volume Rendering Accelerator VisA and its Preliminary Implementation
Sub Title (in English)
Keyword(1) Visualization
Keyword(2) Volume Rendering
Keyword(3) Parallel Processing
Keyword(4) FPGA
Keyword(5) Hardware Accelerator
1st Author's Name Takahiro KAWAHARA
1st Author's Affiliation Kyoto University()
2nd Author's Name Shinobu MIWA
2nd Author's Affiliation Kyoto University
3rd Author's Name Hajime SHIMADA
3rd Author's Affiliation Kyoto University
4th Author's Name Shin-ichiro MORI
4th Author's Affiliation University of Fukui
5th Author's Name Shinji TOMITA
5th Author's Affiliation Kyoto University
Date 2008-01-17
Paper # VLD2007-122,CPSY2007-65,RECONF2007-68
Volume (vol) vol.107
Number (no) 419
Page pp.pp.-
#Pages 6
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